`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:29:24 03/31/2014 
// Design Name: 
// Module Name:    PC_Control 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module PC_Control(pc,
						jump,branch,jump_target,halt,clk,reset);
						
output reg [11:0] pc = 12'd0;
input jump, branch, halt, reset,clk;
input [11:0] jump_target;

always @(posedge clk)
	if(reset)
		pc <= 12'd0;
	else if(halt)
		pc <= pc;
	else if(jump)
		pc <= jump_target;
	else if(branch)
		pc <= jump_target;
	else
		pc <= pc + 1'b1;
		
endmodule
